DES/TDES core

Overview

Key Features

• Standard (1 round per cycle) and Fast (2 rounds per cycle) RTL variants
• FIPS PUB 46-3 and NIST SP 800-67 compliant Single and Triple DES
• 64-bit and 192-bit key words
• ECB, CBC, CFB and OFB modes.
• 16 or 32-bit wide, AMBA 3 APB slave interfaces
• DMA flow control interface
• Verilog RTL

Benefits

• Low gate-count
• FIP 46-3 and NIST SP 800-6 compliant

Block Diagram

Technical Specifications