Triple DES core

Key Features

• Implemented according to the X9.52 standard
• Implementation based on NIST certified DES core
• Also available in CBC, CFB and OFB modes.
• 112 or 168 bits keys supported.
• Both encryption and decryption supported.
• Encryption and decryption performed in 48 clock cycles.
• No dead cycles for key loading or mode switching. .
• Encryption or decryption can start every 16 or 48 cycles, depending on the version.
• Fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx netlist available

Deliverables

• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx netlist available

Technical Specifications