IP Catalog > Security IP > Cryptography IP > Symmetric Encryption IP > DES IP > Triple DES core

Triple DES core

Overview

This core is a full implementation of the Triple DES encryption algorithm. Both encryption and decryption are supported. Simple, fully synchronous design with low gate count.

The X_3DES core is a full hardware implementation of the triple DES algorithm as described in the X9.52 standard, suitable for a variety of applications. 
 
The triple DES algorithm was proposed by IBM when it became clear that the security of the DES had been compromised by advances in computer technology. 
 
Compared to the DES algorithm, the triple DES algorithm provides a much higher level of security. 
 
Each triple DES encryption/decryption operation (as specified in ANSI X9.52) is a compound operation of the DES encryption and decryption operations. 

Key Features

  • Implemented according to the X9.52 standard
  • Implementation based on NIST certified DES core
  • Also available in CBC, CFB and OFB modes.
  • 112 or 168 bits keys supported.
  • Both encryption and decryption supported.
  • Encryption and decryption performed in 48 clock cycles.
  • No dead cycles for key loading or mode switching. .
  • Encryption or decryption can start every 16 or 48 cycles, depending on the version.
  • Fully synchronous design.
  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • Test benches provided.
  • Xilinx netlist available

Block Diagram

Triple DES core Block Diagram

Applications

  • Electronic financial transactions.
  • Secure communications.
  • Secure video surveillance systems.
  • Encrypted data storage.

Deliverables

  • Netlist available for most Xilinx and Altera devices.
  • Synthesizable VHDL or Verilog RTL.
  • Complete HDL testbench.

Technical Specifications

Short description
Triple DES core
Vendor
Vendor Name
Foundry, Node
Xilinx
Availability
now
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