The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypts blocks of data based on the DES encryption standard. In order to accommodate a wide variety of system requirements, the Engine can be generated in two modes: LowLatency and LowGateCount. For a TDES system, three DES cores are instantiated.
AHB DES and Triple DES with DMA
Overview
Key Features
- AHB Master component DMA
- AHB Slave component Register Interface
- DES/TDES modes supported:
- Electronic Code Book (ECB)
- Cipher Block Chaining (CBC)
- Output Feedback (OF)
- Maskable Interrupt
Block Diagram
Deliverables
- Verilog Source
- Complete Test Environment
- AHB Bus Functional Model