3DES

Overview

The 3DES core is a drop-in module that includes the following functions :
• 192-bit key size
• Single or Triple Data Encryption Standard
• Encryption or decryption functions are implemented in the core

Key Features

Implements Triple DES to latest FIPS PUB 46-3
Drop-in module for Spartan-6™, Virtex-6™, Artix-7™, Kintex-7™, Virtex-7™ FPGAs and Zynq™
Single clock
Supports 192-bit key size (168-bit cipher key with 24 additional parity bits)
Supports Single DES Key Parity Checking
Same core can be used for encryption and decryption
ECB (Electronic Code Book) implementation per FIPS PUB 81
DES > 470Mbps @ 125MHz
3DES > 150Mbps @ 125MHz
Full synthesizable RTL VHDL design (not delivered) for easy customization
Design delivered as Netlist

Block Diagram

Applications

3DES core may be used in applications related to MPEG-TS stream encryption, or any other encryption applications.

Deliverables

Datasheet
Netlist for core generation
VHDL top file
VHDL source code: can be delivered as an option under NDA and other specific clauses

Technical Specifications

Availability

Now

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