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Compare 9 Other from 6 vendors (1 - 9)
  • ARIA Crypto Engine
    • Supports a wide selection of programmable ciphering modes
    • Supports encryption & decryption
    • Supports 128-bit, 192-bit & 256-bit key sizes
    Block Diagram -- ARIA Crypto Engine
  • 3GPP Kasumi Accelerators
    • Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
    • Includes key scheduling hardware.
    • Modes Kasumi
    • Algorithms f8 and f9.
    • Fully synchronous design.
    • Low Speed, High Speed versions.
    Block Diagram -- 3GPP Kasumi Accelerators
  • Kasumi Encryption Core
    • Encryption using the Kasumi Block Cipher Algorithm
    • Since all practical uses of Kasumi utilize only the encryption operation, decryption is not part of the core
    • High throughput: up to 3 Gbps in 65 nm process
    • Small size: from 5.5K ASIC gates
    Block Diagram -- Kasumi Encryption Core
  • KASUMI Crypto Engine
    • ASIC and FPGA
    • ETSI specifications compliant
    • Supports:
    • Data interface: AMBA (AXI/AHB) with optional DMA
    Block Diagram -- KASUMI Crypto Engine
  • ARC4 Stream Cipher Accelerators
    • The ARC4-IP-44 (EIP-44) is IP for accelerating the ARC4 stream cipher algorithm (used for legacy SSL & IPsec) up to 5 Gbps @ 600MHz.
    • Designed for fast integration, low gate count and full transforms, the ARC4-IP-44 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
    Block Diagram -- ARC4 Stream Cipher Accelerators
  • GOST (Kuznyechik Cipher) Core
    • Supports all cipher modes defined in NIST SP800-38A: ECB, CBC, CFB1, CFB8, CFB128, OFB and CTR.
  • 3GPP KASUMI f8 and f9 cores
    • Implement 3GPP f8 confidentiality and f9 integrity to 3GPP TS 35.201
    • Both cores support KASUMI ECB mode encryption to 3GPP TS 35.202
    • f8 core generates 64-bit wide keystream output data
    • f9 core performs bit padding of last block and outputs 32-bit MAC-I
  • TwoFish data encryption and decryption
    • TwoFish encrytipn / decryption
    • Supports 128, 192 and 256 bit keys
    • Synthesiable Verilog code
    • Verilog testbench
  • ARC4 Core
    • Offers Encrypt, Decrypt and Key initialisation operations
    • External 8-bit datapath
    • Extremely low area
    • Standard version runs at a rate of 3 clocks per byte
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Semiconductor IP