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RSA

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Compare 21 RSA from 12 vendors (1 - 10)
  • RSA2-AHB Accelerator Core with AHB Interface
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the AHB interface.
    Block Diagram -- RSA2-AHB Accelerator Core with AHB Interface
  • Scalable RSA and Elliptic Curve Accelerator
    • The core implements the exponentiation operation of the RSA cryptography Q = Pk.
    • The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started.
    • Once the operation is complete, the result Q can be read through the interface.
    Block Diagram -- Scalable RSA and Elliptic Curve Accelerator
  • Modular Exponentiation Core
    • Fully synthesisable RTL source code
    • VHDL/Verilog testbench with test vectors
    • User documentation
    Block Diagram -- Modular Exponentiation Core
  • RSA Keygen IP Core
    • RSA Keygen IP Cores perform key generation in compliance with the RSA Key Pair Generation specifications defined in 'FIPS 186'.
    • This standard specifies methods for generating RSA key pairs.
    • RSA Keygen IP Cores support key pair generation up to 4096 bits.
    Block Diagram -- RSA Keygen IP Core
  • RSA IP Core
    • RSA IP Cores perform digital signature generation and verification in compliance with the RSA (Rivest-Shamir-Adleman) Digital Signature Algorithm specifications defined in 'FIPS 186'.
    • This standard specifies methods for digital signature generation and verification using the RSA Digital Signature Algorithm.
    • RSA IP cores support bit lengths from 256 to 4096.
    Block Diagram -- RSA IP Core
  • RSA Public Key Exponentiation Accelerator
    • Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration)
    • Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
    • Support for RSA binary fields of configurable bit sizes up to 2048
    • Microprocessor-friendly interface
    Block Diagram -- RSA Public Key Exponentiation Accelerator
  • RSA/ECC Public Key Accelerators with TRNG and AHB
    • Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
    • Public key signature generation, verification and key negotiation with little involvement of host
    • NIST CAVP compliant for FIPS 140-3
    Block Diagram -- RSA/ECC Public Key Accelerators with TRNG and AHB
  • RSA-ECC High-Performance Multi Public Key Engine
    • RSA, ECC and more
    • > 1 GHz in 16nm
    Block Diagram -- RSA-ECC High-Performance Multi Public Key Engine
  • Public Key Crypto Engine
    • ASIC & FPGA
    • RSA, ECC and more
    • 100% CPU offload
    • DPA countermeasures
    Block Diagram -- Public Key Crypto Engine
  • Asymmetric Public Key Cryptography IP
    • Constant time of the basic arithmetic unit: protection against timing attacks.
    • Regular modular exponentiation (RSA): protection against SPA.
    • Regular ECSM: protection against SPA.
    • Protection against CPA and collision attacks.
    • Protection against Address-bit CPA.
    • Protection against fault attacks.
    Block Diagram -- Asymmetric Public Key Cryptography IP
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