Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”.
The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification.
RSA2-AHB implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.
RSA2-AHB targets compact embedded designs with an ARM AHB bus. Higher performance is available from the RSA5 scalable family of cores.
The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started. Once the operation is complete, the result Q can be read through the AHB interface.
Options
The core comes in a variety of options:
- Multiplication option (CRT) provides an interface to accelerate the Chinese Remainder Theorem in hardware. Without this option, the default exponentiation-only (E) core still permits the use of the CRT, but requires some CPU support.
- Diffie-Hellmann (-DH) option accelerates an entire Diffie-Hellmann algorithm. Without this option, the DH operations requires some CPU support
- Digital Signature (DSA) option accelerates an entire Digital Signature algorithm. Without this option, the DH operations requires some CPU support
