Tcp IP

Increase your TCP and UDP Network actual performance by up to 600%
Built around Proven and Mature TCP and UDP technology since 2009.
40G: In production. Performed Live demo of 40G at Super Computing 2015
Qualified on Altera/Intel and Xilinx. FPGA Subsystems Solutions available now
First company to implement and deliver Full TCP Stack in High performance FPGA in 2009.

NVMeTCP IP is the standalone host side NVMe Over Fabric (NVMe/TCP) controller with no CPU and external memory required. Enabling very high-performance remote access to NVMe-oF Storage Server by simple user logic.
Greatly reduce design complexity and development time. Allowing your FPGA Card/Board to get access to the existing NVMe-oF storage infrastructure remotely and directly over FPGA’s network interface with maximum possible performance.

The TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU.
Generally, TCP processing is so complicated that expensive high-end CPU is required.
TOE-IP core series built by pure hardwired logic can take place of such extra CPU for TCP protocol management.

The TCP Endpoint implements a full, reliable streaming network stack in FPGA logic.
It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces by opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.

Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
Eighth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
All stages of Full TCP stack implemented in High performance hardware

Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera
FPGAs or Structured/ASIC flow.
Eighth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
All stages of Full TCP stack implemented in High performance hardware

INT 1011 is the only SOC IP Core that implements a full 1G bit TCP Stack in Handcrafted, Ultra Low Latency and Very High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation.
INT 2011 is the only SOC that integrates 1G TOE + 1 GEMAC + Host interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications.

Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
Fourth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and TCP protocol proven.

Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
Seventh Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and mature TCP protocol offload implementation
All stages of Full TCP stack implemented in High performance hardware