INT 20012 is the only SOC IP Core that implements a full 10G bit TCP Stack in Handcrafted, Ultra-Low Latency and Very High Performance, Innovative, Flexible and Scalable architecture which can also be easily customized for end product differentiation. It provides the lowest latency and highest performance in the industry. No exceptions…..
INT 20012 is also the only SOC that integrates 10G TOE + 10 GEMAC + Host + PCIe/DMA interfaces in the smallest logic footprint. It is highly flexible that is customizable for layer-3, layer 4-7 network infrastructure and network security systems applications. It is recommended for use in, among others, high performance Cloud Servers, Web Servers, Application servers, NICs, SAN/NAS and data center equipment design applications. It provides key IP building blocks for very high performance 10-Giga bit Ethernet ASIC/ASSP/FPGAs.
INT 20012 has built in advanced architectural flexibility that provides capability for enterprises to differentiate their Network security and Network infrastructure appliances from others and customize them for their specific design application.
INT 20012 can process TCP/IP sessions as client/server in mixed session mode for Network equipment and in-line network security appliances, simultaneously, at 10-G-bit rate. This relieves the host CPU from costly TCP/IP software related session setup/tear down, data copying and maintenance tasks thereby delivering 10x to 20x TCP/IP network performance improvement when compared with TCP/IP software.
10 G bit TCP Offload Engine + PCIe/DMA SOC IP
Overview
Key Features
- Highly customizable hardware IP block. Easily portable to ASIC flow, Xilinx/Altera FPGAs or Structured/ASIC flow.
- Fourth Generation TOE and System Solutions provide ‘Ultra-Low Latency’ and Ultra-High Performance with highest TCP bandwidth in Full Duplex. Network Tested and TCP protocol proven.
- Ultra-Low Latency through 10 G TOE = less than 100 ns
- Ultra-High Throughput, Full Duplex: Receives and Sends sustained large TCP payloads, depending upon remote server/client’s capability
- Fully Integrated and tested on Altera/Xilinx FPGAs; TOE+MAC+PCIe/DMA+Host_I/F SoC IP bundle
Block Diagram
Technical Specifications
Related IPs
- 1G TCP Offload Engine TOE +PCIe Very Low Latency (TOE+PCIe)
- 1G TCP Offload Engine TOE Very Low Latency (TOE)
- 10G-16K Sess. TCP + UDP Offload engine (INT-20011-16K)
- 1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
- 1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)
- 25G-1K Sess. TCP + UDP Offload Engine