The TCP Offloading Engine IP core (TOE200G/100G/40G/25G/10G/1G-IP) is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE-IP core series built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for AMD FPGA. It helps you to reduce development time.
200G / 100G / 40G / 25G / 10G / 1G TCP Offloading Engine
Overview
Key Features
- All pure hardware TCP/IP protocol stack
- Support IPv4 protocol
- Support one port connection
- Support Multi-session * TOE200G/100GADV-IP
- Supports Full Duplex communication
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- Simple data & control interface, support AXI4-ST interface * TOE200G/100GADV-IP
- AXI4 stream interface with AMD Ethernet MAC
- Super low-latency DG 10G EMAC-IP for TOE10G-IP core (Option)
- Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
- Reference design is included in IP core product
Block Diagram
Technical Specifications
Related IPs
- UDP 100G / 40G / 25G / 10G / 1G IP core
- 1G TCP Offload Engine TOE +PCIe Very Low Latency (TOE+PCIe)
- 1G TCP Offload Engine TOE Very Low Latency (TOE)
- 1G TCP Offload Engine TOE+MAC+Host_IF Ultra-Low Latency (STOE)
- 1G TCP Offload Engine TOE+MAC+PCIe+Host_IF Ultra-Low Latency (STOE+PCIe)
- 1G to 100G Single-Port MACsec Engine