muNVMe IP Core

muNVMe IP Core integrated with Integrated Block for PCI Express (PCIe hard IP) from Xilinx is ideal to access one NVMe SSD without CPU and external memory such as DDR. In Accordance with two-user interface, two users are allowed to access one NVMe SSD parallelly. Thus, this solution fits the application which needs to record data to NVMe SSD and read some data in different region at the same time. When an Ethernet IP Core is connected to muNVMe IP, the remote host concept can be adapted for transferring and monitoring data progress across Ethernet network.

muNVMe IP implements as host controller to access NVMe SSD following NVM express standard. Physical interface of NVMe SSD is PCIe. The low-layer hardware is implemented by using Integrated Block for PCI Express (PCIe hard IP) from Xilinx.

muNVMe IP supports six NVMe commands, i.e., Identify, Shutdown, Write, Read, SMART, and Flush command with two user interfaces - User#0 I/F and User#1 I/F. User#0 I/F is the interface of NVM#0 module inside muNVMeIP while User#1 I/F is the interface of NVM#1 module. All six commands are supported by NVM#0 (Main) while NVM#1 (Sub) supports only Write and Read command.

For operating each command, User#0 I/F and User#1 I/F consists of two interface groups. First is Control interface for transferring command and the parameters. Another is Data interface for transferring data when the command must have the data transferring. The Control interface and Data interface for Write/Read command use dgIF typeS format. Control interface of dgIF typeS consists of start address and transfer length with asserting the request signal while Data interface of dgIF typeS is the FIFO interface.

SMART and Flush command require the specific interface, called Custom command interface, which consists of Ctm I/F for control path and Ctm RAM I/F for data path. Furthermore, Identify command has its own data interface, named Iden RAM I/F, as shown in Figure 2. All of these specific interfaces are integrated only in User#0 I/F.

Due to two user interfaces, while Write or Read command is operating in NVM#1, some commands can be operating parallelly in NVM#0, i.e., Identify, Write, Read, SMART, and Flush. However, there is one limitation about the parallel operation. Shutdown command must be executed after NVM#0 and NVM#1 return back to be idle. Thus, NVM#0 must not be requested for Shutdown command while NVM#1 operates Write/Read command.

During initialization process or running some commands, error signal may be asserted by muNVMe IP if some abnormal conditions are found. The IP includes the error status to check the more details of error condition. To recover error status, muNVMe IP and SSD must be reset.

There is one limitation about clock frequency of user logic. Transmit packet to PCIe hard IP must be sent continuously until end of packet. Therefore, data must be valid every clock between start of packet and end of packet. To support this feature, user logic clock frequency must be more than or equal to PCIe clock frequency (250 MHz for PCIe Gen3) to have the bandwidth of transmit logic higher than or equal to PCIe hard IP bandwidth.

The reference designs on FPGA evaluation boards are available for evaluation before purchasing.