Pcie IP

Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7

The AXI Bridge for PCIe IP core is the IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.
The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.

The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0.
The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics.

The PCIe 3.0 (Peripheral Component Interconnect Express 3.0) is a computer hardware interface standard that is used to connect various components to a computer's motherboard.
It is the third generation of the PCIe standard and offers increased bandwidth, improved performance, and reduced power consumption compared to its predecessor, PCIe 2.0 Overall, PCIe 3.0 provides faster and more efficient communication between the various components in a computer, including graphics cards, network adapters, and storage devices, resulting in better overall performance.

R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass modes
PCIe 3.0, 4.0, and 5.0 configurations are natively supported
R-Tile also supports up to 16 SerDes channels through a PHY Interface for PCIe (PIPE) 5.1.1 in SerDes Architecture mode.

P-Tile is an FPGA companion tile available on Stratix® 10 DX and Agilex™ 7 FPGA F-Series device that natively supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes.

Stratix® 10 FPGAs incorporate the L/H-Tile chiplets which include a configurable, hardened protocol stack for PCIe that is compliant with PCIe Base Specification 3.0
This Avalon® Streaming Interface Hard IP supports PCIe 1.0, 2.0, and 3.0 data rates and x1, x2, x4, x8, or x16 configurations, including support for SR-IOV functionality.

Agilex™ 5 FPGAs and SoC FPGAs are monolithic designs with integrated high-speed transceivers (GTS) and hardened PCIe controller IP supporting up to PCIe 4.0 x8 configurations for Root Port (RP), Endpoint (EP), and Transaction Layer (TL) bypass modes.
GTS PCIe Hard IP for PCI Express Greatly Simplifies Design Integration for a Broad Range of Applications

The F-Tile Intel® Hard IP supports PCIe* configurations up to 4.0 x16 in Endpoint (EP), Root Port (RP), and Transaction Layer (TL) Bypass Modes
F-Tile serves as a companion tile for Agilex™ 7 devices.