Full compatible with PIPE4.2 interface specification
PCIe PHY
Overview
Key Features
- Support for PCIe3(8.0Gbps)，Backward compatible with 2.5Gbps and 5Gbps for PCIe
- Full compatible with PIPE4.2 interface specification
- Support 16bit and 32bit parallel data bus
- Independent channel power down control
- Supported reference clock input range from 25M to 400M
- Programmable transmit amplitude and FFE
- Implemented Receiver equalization Adaptive-CTLE and DFE to compensate insertion loss
- Integrated on-die termination resistors and IO Pads/Bumps
- Support receiver detection, Beacon signal generation and detection
- Support Spread Spectrum clock generation(optional) and receiving
- Embedded Primary & Secondary ESD Protection
- HBM/MM/CDM/Latch-Up 2000V/200V/500V/100mA
- Silicon Proven in SMIC14SF+/SF++ with 0.8V and 1.8V power supply
- Area: 0.32mm2 per-lane
Technical Specifications
Short description
PCIe PHY
Vendor
Vendor Name
Foundry, Node
SMIC14SF+/SF++
SMIC
Silicon Proven:
14nm