High-performance DSPs designed for floating-point-centric processing with ultra-low energy and small area
Cadence® Tensilica® FloatingPoint KP1/KP6 DSPs provide high-performance floating-point computation throughput with low energy consumption and small area footprint. The configurability and extensibility of Tensilica FloatingPoint KP1/KP6 DSPs give the SoC designers flexibility to configure a floating-point DSP that meets their performance requirements with low energy and small area budgets. Tensilica FloatingPoint KP1/KP6 DSPs are optimized for applications in battery-operated devices, AI/ML, AR/VR, motor control, smart sensors, sensor fusion, ADAS, autonomous driving, etc.
Tensilica FloatingPoint KP1/KP6 DSPs
Overview
Key Features
- VLIW parallelism issuing multiple concurrent operations per cycle
- Xtensa LX Secure Mode
- 128-bit and 512-bit SIMD
- IEEE 754 vector floating-point
- Performance optimized fused multiply-add (FMA)
- 8b/16b/32b/64b integer ALU operations
- Optimized for FFT operations
- Enhanced complex data processing
- Superior auto vectorization support
- TIE for easy extension and further performance enhancement
Applications
- Automotive,
- Communications,
- Consumer Electronics,
- Data Processing,
- Industrial and Medical,
- Military/Civil Aerospace,
- Others
Technical Specifications
Maturity
Available on request