Encoder/Decoder pair that implements the standard IBM® 8b/10b line code for a DC-balanced serial data stream.
The 8b/10b code is a common encoding scheme used for the transmission of serial AC-coupled data with embedded clock over larger distances.
8b/10b Encoder/Decoder
Overview
Key Features
- Supports the standard IBM® 8b/10b line code for a DC-balanced serial data stream
- Supports all standard control symbols - K.28.0 to K.30.7
- Separate encoder and decoder pair
- Fully synchronous design with data input and output valid flags
- Generic parallel input and output data widths
- Error flags indicate control symbol errors and general decoding errors
- Running disparity calculations handled internally
- Fully scalable architecture
- Suitable for use in serial data links of 6 GHz+ on basic FPGA devices
Benefits
- Technology independent soft IP Core
- Suitable for FPGA, SoC and ASIC
- Supplied as human-readable source code
- One-time license fee with unlimited use
- Field tested and market proven
- Any custom modification on request
Block Diagram
Deliverables
- VHDL source-code (or Verilog on request)
- Simulation test bench
- Examples and scripts
- Full pdf datasheet
- One-to-one technical support
- One years warranty and maintenance
Technical Specifications
Foundry, Node
All
Availability
Immediate