HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .
The module is accessed through an APB slave from the host side.
HDLC frame to APB bridge
Overview
Key Features
- Synchronous operation
- 8-bit parallel back-end interface
- Use external RX and TX clocks
- Start and end of frame pattern generation
- Start and end of frame pattern checking
- Idle pattern generation and detection (all ones)
- Zero insertion and removal for transparent transmission
- Abort pattern generation and checking (7 ones)
- Address insertion and detection by software
- CRC generation and checking (CRC-16 or CRC-32 can be used, which is configurable at the code top level)
- Configurable size FIFO buffers for low latency transfer
- Byte aligned data (if data is not aligned to 8-bits, error signal is reported to the backend interface)
- Q.921, LAPD, and LAPB compliant
- APB slave interface for host operations
Block Diagram
Applications
- Communication controllers in networking and telecommunication systems.
- Automotive systems for reliable data transfer (e.g., over CAN or LIN gateways).
- Industrial automation requiring HDLC connectivity with APB-based processors.
Technical Specifications
Related IPs
- AHB to APB Bus Bridge
- AXI to APB Bus Bridge
- JTAG Slave To APB Bridge IIP
- TileLink To APB Bridge IIP
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- PCI to AMBA AHB Host Bridge