The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance. It is used to connect peripherals around the CPU and to replace the Industry Standard Architecture (ISA) bus which can only run up to 8 MHz. The primary benefit is that signals can be transmitted across a minimum of seven traces for an LPC bus versus 52 traces for an ISA bus. This relieves the pressure of routing on the often-congested motherboard and at the same time improves the overall system integrity.
Low Pin Count (LPC) controller verification IP
Overview
Key Features
- LPC Interface Increase the memory space from 16MB on the X-bus to 4GB to allow BIOS sizes much greater than 1MB, and other memory devices outside of the traditional 16MB range.
- Synchronous design. Much of the challenge of an X-bus design is meeting the different, and in some cases conflicting, ISA timings. Make the timings synchronous to a reference well known to component designers, such as PCI.
- Perform the same cycle types as the X-bus: Memory, I/O, DMA, and Bus Master.
- Reduce the cost of traditional X-bus devices.
- Support desktop and mobile implementations.
- Ability to support a variable number of wait-states.
Block Diagram
Deliverables
- LPC VIP – UVM Environment
- Userguide
- Regression Script