AMBA AHB / APB IP
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212
AMBA AHB / APB IP
from 26 vendors
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AHB/AXI/Wishbone DMA Controller
- The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
- The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.
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Verification IP for AMBA
- AMBA® ACE and CHI coherent interconnect technologies enable an entirely new class of high-performance datacenter applications in areas of machine learning, network processing, storage off-load, in-memory database, and 4G/5G wireless technology.
- Processor architectures and accelerators can now seamlessly operate over cache coherent intercon nects using the right combination of general-purpose processors and heterogeneous acceleration devices, such as FPGAs, GPUs, network/ storage adapters, intelligent networks, and custom ASICs.
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SPI to AHB Bridge
- The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
- On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
- The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.
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10/100 Mbit Ethernet MAC
- The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
- The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
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CAN 2.0 Controller with DMA
- GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.
- The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.
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AMBA AHB Direct Memory Acess (DMA) Controller
- Multiple independent DMA channels with direct AHB bus interface.
- DMA transfers between AHB memory devices and I/O ports.
- Scatter-gather allows DMA to merge multiple data source to contiguous space.
- Supports both hardware initiated transfer and software initiated transfer.
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AMBA AHB Bus Master
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to any slave devices on the AHB Bus.
- User specified single or burst data access on the AHB interface and user interface.
- Handles wait state insertion by any slave devices.
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AMBA AHB Bus Slave
- Supports AHB bus interface to the ARM CPU.
- User interface designed for high speed access to two sets of on-chip or off-chip modules.
- Four write buffers to process posted write.
- Dual read buffers to process CPU read.
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AMBA AHB to PCI Host Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Supports AHB bus protocol.
- Downstream access transfer from AHB bus to PCI bus.
- Upstream access transfer from PCI bus to AHB bus.
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AMBA ATB Verification IP
- Compliant to AMBA 5 ATB (aka ATB-C), AMBA 4 ATB (aka ATB v1.1) and AMBA 3 ATB (aka ATB v1.0) Protocol.
- Parameterized address and data width and hence capable of configuring all possible ATB and TPIU bus widths.
- Bus Monitor is easy to Plug-in and is compliant with standard specifications.
- Support for static and dynamic protocol checks.