The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options. These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.
Up to 16 independent AXI Stream Slaves write DMA data to the connected AXI Slaves. Up to 16 AXI Stream Masters read DMA data from the connected slaves and present it to the user logic. Each channel operates in its own address map. This IP core targets continuous data streaming applications (i.e. data acquisition, Video and DSP applications) with AXI Stream interfaces and is well suited for standard AXI4 Slaves including DDR Memory Interfaces or the AMD ZynqTM devices. A sophisticated Linux kernel mode device driver allows easy data access from user mode.
