The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports. Only single control lines are re-synchronized between the two clock domains ensuring hazard free operation. The requirement for Gray coded addressing is thus eliminated. A wide range of clock frequencies and relative frequencies between read and write ports are fully tolerated. The interface signals are fully synchronous to their respective domains; no asynchronous signals are present on either side. Only reset may be asynchronous in that it is asserted asynchronously and synchronized internally to both clock domains to again ensure hazard free operation.
Asynchronous FIFO with configurable flags and counts
Overview
Key Features
- Fully Synthesizable RTL - Verilog
- Static Timing Analysis compatible
- Dual-port inferred RAM architecture
- Configurable width and depth
- Standard FIFO handshake interface
- Insensitive to relative clockrates
- Flags or depth values on each port
Block Diagram
Applications
- Re-synchronizing data between clock domains
- General purpose buffering
Technical Specifications
Short description
Asynchronous FIFO with configurable flags and counts
Vendor
Vendor Name
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