The FIFO-CAM controls are designed to operate over a wide range of clock frequencies. The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
The contents of the FIFO buffer may be searched by a applying a search term to the ST input. If a match is found a bit-map of those locations that match are output on the EQ lines. This interface is asynchronous there being no registers within this datapath.
