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DDR5 Controller IP

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Compare 51 DDR5 Controller IP from 15 vendors (1 - 10)
  • CXL memory expansion
    • Turn key solution: compression, compaction, memory management
    • Automatic compressed memory tier
    • Multi-instance support to match interface throughput
    • Cache line granularity decompression for highest read performance (proprietary algorithm)
    Block Diagram -- CXL memory expansion
  • MRDIMM DDR5 & DDR5/4 PHY & Controller
    • The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • It supports all JEDEC DDR5/4 SDRAM components in the market
    Block Diagram -- MRDIMM DDR5 & DDR5/4 PHY & Controller
  • Memory Controller
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- Memory Controller
  • DDR5 Serial Presence Detect (SPD) Hub Interface
    • The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus
    • This SPD5 has Two wire serial interface like SCL, SDA
    •  
    Block Diagram -- DDR5 Serial Presence Detect (SPD) Hub Interface
  • DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD03)
    • The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs
    • Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs
    • It also creates a BCOM bus which controls the data buffers for LRDIMMs
    •  
    Block Diagram -- DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD03)
  • DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD01)
    • The DDR5RCD01 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs
    • Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs
    • It also creates a BCOM bus which controls the data buffers for LRDIMMs
    •  
    Block Diagram -- DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD01)
  • AP Memory UHS PSRAM Controller
    • This controller supports AP Memory’s UHS series of high speed PSRAM devices which can clock frequencies of upto 1066 MHz.
    • This controller enables smooth integration of APMemory’s UHS OPI PSRAM memory device chips into various new-gen devices made with mobile and wearable low power SoCs’.
    • This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.
    Block Diagram -- AP Memory UHS PSRAM Controller
  • Winbond HyperRAM Controller
    • The HyperRAM controller supports Winbond’s HyperBus based HyperRAM devices
    • This controller enables smooth integration of Winbond’s HyperBus HyperRAM memory chips into various new-gen SoCs’.
    Block Diagram -- Winbond HyperRAM Controller
  • Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
    •  
    • The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a highly flexible and configurable design that supports RLDRAM2, RLDRAM3 and JEDEC compliant DDR5, DDR4 3DS, DDR4, DDR3, LPDDR3, LPDDR3 and LPDDR2 memories.
    • It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities
    Block Diagram -- Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
  • GDDR6 Controller
    • Supports up to 24 Gb/s per pin operation
    • Can handle two x16 GDDR6 channels with one controller or independently with two controllers
    • Supports x8 or x16 clamshell mode
    • Queue-based interface optimizes performance and throughput
    • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
    • Automatic retry on transactions where EDC error detected
    Block Diagram -- GDDR6 Controller
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