DDR5 REGISTERING CLOCK DRIVER (RCD) IP - (DDR5RCD03)

Overview

The DDR5RCD03 is a registering clock driver used on DDR5 RDIMMs and LRDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. It also creates a BCOM bus which controls the data buffers for LRDIMMs.

Key Features

Compliance as per JEDEC's JESD82-513
In I3C mode, SCL Operating speed 12.5MHz as Maximum
DDR5 server speeds up to 6000MT/s
Dual channel with each channel being 32 bits wide for data
Supports power saving mechanisms
Supports rank 0 & rank 1 DIMM configurations
Loopback and pass-through modes
BCOM sideband bus for LRDIMM data buffer control
Support In-band Interrupt
Packet Error check(PEC)
CCC Packet Error Handling
Error log register
Parity Error Handling Support
Interrupt Arbitration
I2C Fast-mode Plus (FM+) and I3C Basic supported
Support switch from I2C mode to I3C Basic
I2C Mode, Supports
- Block Write
- Block Read
- Byte Write
- Byte Read
I3C Mode, Supports
- Block Write
- Block Read
Clearing Status Registers
JESD82-513 specification compliance
I3C Basic Common Command Codes (CCC)
- DEVCTRL
- SETHID
- SETAASA
- ENEC
- DISEC
- RSTDAA
- DEVCAP
- GETSTATUS

Block Diagram

Deliverables

Verilog Source Code
User Guide
IP Integration Guide
Simulation Script
Synthesis Script
Encrypted Verification Test-bench Environment
cocotb Verification Environment
Basic Test-suite
Firmware code

Technical Specifications

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