DDR5 IP

Compare 499 DDR5 IP from 24 vendors (1 - 10)

CXL memory expansion
- Turn key solution: compression, compaction, memory management
- Automatic compressed memory tier
- Multi-instance support to match interface throughput
- Cache line granularity decompression for highest read performance (proprietary algorithm)
PSRAM/RPC PHY & Controller
- The DDR IP Mixed-Signal MR PSRAM PHY and RPC PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM/RPC devices
- It is optimized for low-power and high-speed applications with robust timing and small silicon area
- The PSRAM PHY supports AP memory UHS/OPI PSRAM components on the market, and the RPC PHY supports ETRON components on the market
MRDIMM DDR5 & DDR5/4 PHY & Controller
- The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
- It is optimized for low-power and high-speed applications with robust timing and small silicon area
- It supports all JEDEC DDR5/4 SDRAM components in the market
GDDR6X/6 Combo PHY & Controller
- The GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20Gbps per pin for PAM2 GDDR6 mode and 24Gbps for PAM4 GDDR6X mode
- The GDDR6X/6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits per memory device
- With a maximum speed of 20/24Gbps per pin, The GDDR6X/6 Combo PHY delivers a peak bandwidth of up to 80GB/s or 96GB/s per memory device
GDDR6 PHY IP for 12nm
- JEDEC JESD250 compliant GDDR6 support
- X16 mode, X8 mode, and pseudo-channel mode
- Low frequency RDQS mode support
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
LPDDR5X/5/4X/4 combo PHY at 7nm
- Compliant with JEDEC JESD209-5B for LPDDR5X/5/4X/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
LPDDR5X/5/4X/4 PHY IP for 12nm
- Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports up to 4 ranks
- Multiple frequency states
Memory Controller
- JEDEC GDDR6 standard JESD250B
- Fast frequency switching
- Flexible Configuration
DDR5 Serial Presence Detect (SPD) Hub Interface
- The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus
- This SPD5 has Two wire serial interface like SCL, SDA