CXL memory expansion
Overview
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with minimal impact to latency and badwidth. DenseMem is available as an area and power efficient drag and drop IP block portable across the latest process nodes.
Key Features
- Turn key solution: compression, compaction, memory management
- Automatic compressed memory tier
- Multi-instance support to match interface throughput
- Cache line granularity decompression for highest read performance (proprietary algorithm)
Benefits
- Standards
- Protocol: CXL 2.0, 3.0, 3.1, cxl.mem
- Compression: LZ4, ZID (proprietary)
- AMBA interface: AXI4, CHI
- Architecture
- Transparent addressing to host
- Arbitrary cache line read/ write
- Bridge to cxl.mem, optionally to cxl.io
- Support for DCD, optional custom interface
- Type 3 device support, NUMA based memory tiering
Deliverables
- FPGA evaluation license
- Encrypted IP delivery (Xilinx)
- HDL Source Licenses
- Synthesizable System Verilog RTL (encrypted)
- Implementation constraints
- UVM testbench (self-checking)
- Vectors for testbench and expected results
- User Documentation
Technical Specifications
Maturity
Tape-out
Availability
Immediate
Related IPs
- On-chip memory expansion
- Fast Access Controller – a plug-and-play IP solution for fast embedded Flash Programming and Memory Testing
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core
- DDR1 DDR2 SDRAM Memory Controller
- PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
- Multi-Port Memory Controller (DDR/DDR2/SDRAM)