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MIPI SoundWire I3S Verification IP

Overview

The SmartDV Verification IP (VIP) for MIPI SoundWire I3S provides an efficient and simple way to verify the MIPI SoundWire I3S protocol bus. The SmartDV VIP for MIPI SoundWire I3S is fully compliant version Draft v0.4r06 MIPI SoundWire I3S Bus Specification.

MIPI SoundWire I3S Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

MIPI SoundWire I3S Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

  • Full MIPI SoundWire I3S Master, Slave and Monitor functionality
  • Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
  • Supports system with one master and one or more slaves (upto 8 slaves).
  • Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.
  • Supports reset and link power management.
  • Supports 8b/10b encoding and decoding.
  • Supports the following transfer types,
    • Info transfer
    • Read transfer
    • Write transfer
    • Multicast write transfer
    • Multicast commit transfer
    • Multi Phase read transfer
  • Supports all control data and command formats in master and slave.
  • Supports Transport of payload data.
  • Supports Timing information from the Master enabling the Slave both to send and receive data bits and to generate audio sampling events.
  • Supports for multiple channels and both PDM and PCM data encodings.
  • Supports Row based structure of the bitstream.
  • Supports for low latency transmission.
  • Supports In-band signaling of interrupt conditions.
  • Supports In-band signaling of wake-up requests.
  • Supports System-wide stream synchronization.
  • Supports Embedded command channel for reading and writing control parameters and reporting status.
  • Supports clock data recovery.
  • Supports Jitter insertion.
  • Supports below transport and protocol errors,
    • Bad symbol error
    • Bad token error
    • Bad HD10 token Error
    • CRC error
    • Unexpected token protocol error
    • Unexpected phase protocol error
  • Status counters for various events in bus.
  • Detects and notifies the test bench of all protocol and timing errors.
  • Callbacks in master, slave and monitor for user processing of data.
  • MIPI Soundwire – I3S Verification IP comes with complete test suite to test every feature of MIPI Soundwire – I3S specification.
  • Functional coverage for complete MIPI Soundwire – I3S features.

Benefits

  • Faster testbench development and more complete verification of MIPI SoundWire I3S designs.
  • Easy to use command interface simplifies testbench control and configuration of master and slave.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

Block Diagram

MIPI SoundWire I3S Verification IP Block Diagram

Deliverables

  • Complete regression suite containing all the MIPI SoundWire I3S testcases.
  • Examples showing how to connect various components, and usage of Master,Slaves and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Technical Specifications

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