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Ethernet PHY IP

Welcome to the ultimate Ethernet PHY IP hub! Explore our vast directory of Ethernet PHY IP

The Ethernet PHY IP cores encode data frames for transmission and decode received frames with a specific modulation speed of operation, transmission media type and supported link length.

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Search (65)
Compare 65 Ethernet PHY IP from 14 vendors (1 - 10)
  • Block Diagram -- DSP 10/100 100B-TX Ethernet PHY
  • Multi-Rate Ethernet PHY FPGA IP
    • The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device reconfiguration
    • This IP allows the creation of a 1G to 10G configuration that allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G.
    Block Diagram -- Multi-Rate Ethernet PHY FPGA IP
  • 1G/10Gb Ethernet PHY Intel® FPGA IP
    • The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding sublayer (PCS) and the higher data rate 10G PCS with an appropriate physical medium attachment (PMA)
    • The Standard PCS implements the 1GbE protocol as defined in Clause 36 of the IEEE 802.3 2005 Standard and also supports auto-negotiation as defined in Clause 37 of the IEEE 802.3 2005 Standard
    • The 10G PCS implements the 10G Ethernet protocol as defined in the IEEE 802.3 2005 standard.
    Block Diagram -- 1G/10Gb Ethernet PHY Intel® FPGA IP
  • Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
    • The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instantiate both the hard standard physical coding sublayer (PCS) and the higher performance hard 10G PCS, and hard physical medium attachment (PMA) for a single Backplane Ethernet channel
    • It implements the functionality described in the IEEE 802.3ap-2007 standard
    • Because each instance of the 10GBASE-KR PHY IP core supports a single channel, you can create multichannel designs by instantiating more than one instance of the core.
    Block Diagram -- Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
  • XAUI PHY Intel® FPGA IP
    • The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection
    • This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Intel® FPGA to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.
    Block Diagram -- XAUI PHY Intel® FPGA IP
  • 10GBASE-R PHY Intel® FPGA IP
    • The 10GBASE-R PHY Intel® FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces.
    Block Diagram -- 10GBASE-R PHY Intel® FPGA IP
  • CEI-6G-SR PHY
    • Low Risk
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- CEI-6G-SR PHY
  • XAUI PHY
    • Very low output jitter
    • Receiver equalization for enhanced jitter tolerance
    • Programmable TX levels with multiple post-cursor emphasis options
    • Automatic driver/receiver impedance calibration
    Block Diagram -- XAUI PHY
  • Ethernet 10/100 PHY
    • Supports MII.
    • Auto-MDX
    • 10/100Mbs operation supported
    • Full/half duplex operation
    Block Diagram -- Ethernet 10/100 PHY
  • OPEN Alliance TC14 10BASE-T1S PMD Controller
    • The CT25207, in combination with the CT25203, implements a complete OPEN Alliance TC14 10BASE-T1S PMD Interface.
    • The IP also includes a MDIO slave that allows access to Clause 22 PMD standard registers and to IP specific registers (both embedded in the IP) and to custom registers (to be placed outside the IP).
    Block Diagram -- OPEN Alliance TC14 10BASE-T1S PMD Controller
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