Simulation VIP for eUSB2V2

Overview

Best-in-class eUSB2v2 Verification IP for your IP, SoC, and system-level design testing.

The Verification IP (VIP) for eUSB2v2 is a complete VIP solution for the embedded USB2 (eUSB2) Version 2.0. It provides a mature and comprehensive verification IP (VIP) for the eUSB2v2 protocol. Incorporating the latest protocol updates, the eUSB2v2 VIP is not only a complete bus functional model (BFM) for the eUSB2v2 DUT, but it also provides integrated automatic protocol checks and coverage models.

This VIP for eUSB2v2 provides support for any agent in native mode: Host (eDSPn) or device (eUSPn). It supports eUSB2v2 operational high speed (960Mbps to 4.8Gb/s). eUSB2v2 link can be configured as symmetric or asymmetric, each with multiple bit rate options (960Mbps to 4.8Gb/s in both transfer directions). The eUSB2v2 VIP is designed to make it easy to integrate in testbench for IP, system-on-chip (SOC), and sub-system level. The eUSB2v2 VIP helps reduce the time to test by accelerating verification closure and ensuring end-product quality.

The VIP for eUSB2v2 runs on all major simulators. It supports all main verification languages, such as Verilog, System Verilog, and e, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specifications: eUSB2v2 1.0

Key Features

Supported DUT Types: All eUSB2v2-compliant DUT types in host (eDSPn) or device (eUSPn) mode
Transaction Types: All types of transfers: bulk, control, interrupt, and isochronous transactions
Enumeration: Provides a complete USB protocol hierarchy enumeration process for device models from Host
Operational Speed: Operates at high speed (960Mbps to 4.8Gb/s) and support symmetric/asymmetric data rate
Reset Signaling: Supports high-speed chirp handshake
Suspend/Resume: Supports suspend, resume, remote wake-up, and low-power management (LPM)
Transaction and Packet Checks: Checks for all transaction and packet rules including inter-packet gap and propagation delays
Protocol Features
- Support symmetric/asymmetric mode: All HSx data rate for upstream and downstream supported
- Support scrambling
- Support link bring up
- Support for jitter handling
- Support for port reset in all states
Translator: Digital translator available for sending eUSB2v2-compliant traffic
Register interface:
- Support to change the severity (Error, Warning, Info) of the protocol assertions
- Support to initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on
- Support to control the functionality such as end-point buffers, chirp sequence, and clock frequency
- Support to store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench
- Support to insert error injections
- Support to initiate go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)
Predefined Error Injections
- Device drives Port Reset during POR
- Host drive ED+ as 1 instead of driving SE1 in Port Reset
- Device corrupts the ACK in Port Configuration
- Device drives invalid Connect Signal depending on the speed of operation
- Device drives invalid ping
- Host does not send an EOP
- Host drives J signal instead of K during the resume operation
- Host does not drive Resume signal after Remote wakeup from device
- Host sends corrupted EOP to the device

Benefits

Supports testbench languages for System Verilog, UVM, OVM, and e
Runs on all major simulators
Generation of constraint-random bus traffic
Verify all agent types: Host (eDSPn) or Device (eUSPn)
Dynamic activation and reconfigure the VIP attributes anytime during the simulation
Built-in verification plan, protocol checks, and coverage model
Callback access at multiple TX and RX queue points for Scoreboard and data manipulation

Block Diagram

Technical Specifications

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