IP for TSMC

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Compare 262 IP for TSMC from 15 vendors (1 - 10)
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  • 3nm
  • LPDDR6/5X/5 PHY V2 - TSMC N3P
    • The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
    • With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
    • LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
    • The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications
    Block Diagram -- LPDDR6/5X/5 PHY V2 - TSMC N3P
  • LPDDR6/5X/5 PHY - TSMC N3P
    • The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
    • With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
    • LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
    • The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications
    Block Diagram -- LPDDR6/5X/5 PHY - TSMC N3P
  • LPDDR6/5X/5 PHY V2 - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
    • With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
    • LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
    • The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications
    Block Diagram -- LPDDR6/5X/5 PHY V2 - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
  • Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
    • 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
    • It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.  
    Block Diagram -- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V)  -  TSMC 3nm N3P
  • Ultra-Low-Power Process, Voltage, and Temperature Monitor in 3nm
    • The ODT-PVT-ULP-001C-3nm is an ultra-low power temperature, voltage and process monitor designed in a 3nm CMOS process.
    • This IP operates over the entire temperature range of -40°C to 150°C.
    • The temperature monitor achieves ±4C temperature accuracy without trim and ±1C temperature accuracy after a single room temperature trim.
    • The voltage monitor supports four differential or singleended inputs with a voltage range up to ±0.75V.
    Block Diagram -- Ultra-Low-Power Process, Voltage, and Temperature Monitor in 3nm
  • Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
    • The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
    • This 7-bit, 64GSPS ADC supports ac-coupled input signals up to Nyquist and features a full-scale range of 0.45Vpp differential, excellent dynamic performance, and low noise operation.
    Block Diagram -- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC	on 3nm
  • 12bit, 400 MSPS ADC Ultra Low Power
    • Ultra high-performance low-power ADC
    • Integrated input buffer
    • 12-bit ADC resolution
    • Sampling rate of 500MSPS
    • Fully differential operation
    • 0.8Vpp differential input signal range
    Block Diagram -- 12bit, 400 MSPS ADC Ultra Low Power
  • PVT Sensor Subsystem
    • Start-up time: Typ 20us 
    • Current consumption: Max 25uA 
    • Industry standard digital interface 
    • Fully integrated macro 
    • Standard AMBA APB interface
    Block Diagram -- PVT Sensor Subsystem
  • Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
    • TSMC 28nm 28HPC CMOS
    • High accuracy temperature and voltage measurements
    • Process detector for all-voltage threshold MOS transistors
    • Up to 16 remote temperature/voltage sensors
    Block Diagram -- Process/Voltage/Temperature Sensor (Supply voltage 1.8V/0.9V)
  • 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
    • Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
    • The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
    • VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
    Block Diagram -- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
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