Special IP for SMIC
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49
Special IP
for SMIC
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PAD - SMIC 110nm generic
- Standard I/O size is low to 78um*32um
- HBM ESD: ±2000V; MM: ±200V; CDM: ±500V; LU: 150mA
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MCU PAD - SMIC 55nm Eflash
- 5V/1.8V/3.3V/1.2V power supply can be used, not only compatible with normal 1.8V/3.3V
- powering system, and also 5V or lithium battery powering system
- ? Including ultra-low leakage MCU I/O total solution
- ? Supports 1.2V core voltage power off, and get ultra-low leakage
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MCU PAD - SMIC 55nm Eflash
- 1.8V/3.3V/1.2V power supply can be used
- ? Including ultra-low leakage MCU I/O total solution
- ? Supports 1.2V core voltage power off, and get ultra-low leakage
- ? Provides a wide variety of interrupt I/O for customers to easily communicate with outside
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3.3V 32 KHz RTC and Programmable 100MHz Oscillator I/O Pad Set
- Designed to use a 32.786 kHz external crystal for Real Time Clock applications.
- Optimized for low power, stability and minimum jitter
- Characterized with crystal loading capacitors ranging from 4 pF to 25 pF.
- Power-down and bypass modes
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SMIC 55nm LP Multiple Power Supply IO library
- SMIC55nm low power 1.2v/2.5v process
- Supports a broad range of IO power supply from 1.8V to 3.3V
- Supports configurable output driving capability under different IO supply voltage
- Supports configurable pull up and pull down resistor
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MCU PAD - SMIC 55nm Eflash
- Supports 1.2V off with 3.3V/2.5V latches
- Low power crystal oscillator amplifier, the current of 32.768KHz crystal is lower than 200nA
- Standard I/O size is low to 70um*128um
- HBM ESD: >2000V; MM: ±200V; CDM: ±500V; LU: 150mA
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SMIC 65nm LL DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application;
- SMIC 65nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 40um * 270um with DUP stagger bonding pads;
- Work IO voltage: 1.2V/1.5V/1.8V;
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SMIC 55nm LL LPDDR interface for DRAM application
- LPDDR interface for DRAM application;
- SMIC 55nm Logic Low Leakage 1P10M Salicide 1.2V/1.8V/2.5V Process;
- Cell Size (Width * height) 35um * 174um with DUP stagger bonding pads;
- Work voltage: 1.8V;
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SMIC 130nm LL IO
- SMIC 0.13um Logic 1P8M Salicide 1.2/3.3v Process;
- Suitable for 6,7 and 8 layers application;
- 268um * 271um & 67um*131um including pads;
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SMIC 130nm G SSTL2 and LVTTL combo I/O library
- SMIC 0.13um SSTL2 and LVTTL combo I/O library
- SMIC 0.13um Logic 1P8M Salicide 1.2V/3.3V Process
- Suitable for 6,7 and 8 layers application
- Compatible with SP013D3