SMIC18 General process, Multi-Voltage IO, High ESD perfermance

Overview

SMIC18 General process, Multi-Voltage IO, High ESD perfermance

Key Features

  • SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V process
  • Support configurable output driving capability with selective slew rate control
  • Support configurable pull up and pull down resistor
  • Support both CMOS and Schmitt input
  • Support both inline and staggered IO pads
  • Suitable for four, five, six metal layers physical design
  • Easy interface with VeriSilicon SMIC 0.18um process standard I/O libraries
  • High ESD perfermance:7KV

Deliverables

  • Databook in electronic format
  • Verilog models and Synopsys synthesis models
  • Candence Silicon Ensenble Abstracts (LEF), Avanti! Apollo data, GDS II, LVS netlist

Technical Specifications

Foundry, Node
SMIC, 0.18um
Maturity
Silicon Proven
SMIC
Pre-Silicon: 180nm EEPROM , 180nm G , 180nm LL
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Semiconductor IP