VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell
Overview
VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple DUP I/O Cell (05) Library developed by VeriSilicon supports power/ground pads, bi-directional I/O, IU (bi-directional I/O with pull-up only), open drain I/O and OSC pad. This library supports DUP I/O pads. It can be easily assembled with VeriSilicon Generic I/O library.
Key Features
- Process: Semiconductor Manufacturing International Corporation (SMIC) 0.13um Logic Salicide 1.2/3.3V process
- Supply voltage:
- ----1.35V~3.6V for I/O power supply
- ----1.2V core power supply
- Power on sequence control for low leakage
- Configurable output strength(2mA~24mA)
- Selective output slew rate control
- Configured OSC cell which provides clock signal from 32KHz to 30MHz
Technical Specifications
Foundry, Node
SMIC, 0.13um
Maturity
Available on request
SMIC
Pre-Silicon:
130nm
EEPROM
,
130nm
G
,
130nm
LL
,
130nm
LV
Related IPs
- VeriSilicon SMIC 0.13um 1.2V/3.3V SSTLCOMBO_02 I/O Cell Library
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O 01C Library
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
- VeriSilicon SMIC 0.13um 1.2V/3.3V Multiple I/O Cell
- VeriSilicon GSMC 0.18um 1.8V/3.3V Multiple DUP I/O
- VeriSilicon CHRT 0.13um 1.2V/3.3V DUPIO_01 Library