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PCI IP for SMIC

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Search (12)
Compare 12 PCI IP for SMIC from 6 vendors (1 - 10)
  • PCIe 3.1 Controller with AXI
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
    Block Diagram -- PCIe 3.1 Controller with AXI
  • PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
  • USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
    • Support for SATA3(6.0Gbps) ,USB3.0(5Gbps) and PCIe3(8.0Gbps),
    • Backward compatible with 1.5Gbps, 3.0bps for SATA
    • Backward compatible with 2.5Gbps and 5Gbps for PCIe
    • Full compatible with PIPE4 interface specification
  • PCIe 2.0 PHY in SMIC (40nm, 28nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
  • PCIe Gen2 PHY
    • ? 5-Gbps data transmission rate
    • ? PIPE3-compliant transceiver interface, configurable using soft Physical Coding Sublayer (PCS)
    • layer above hard macro PHY
    • ? Supports 8-bit interface at 500-MHz operation
  • PCIe 2.1 PHY(12nm,14nm, 16nm, 28nm, 40nm, 55nm)
    • Fully compliant with PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
  • SMIC 0.25um 2.5V/3.3V PCI I/O Cells Library
    • SMIC 0.25um Logic 1P5M Salicide 2.5V/3.3V process
    • 2.5V core and 3.3V external interface
    • Meets the revision 2.2 of PCI local bus specification
    • Cell count: 6 cells
  • SMIC 0.18um PCI I/O Cells DUP Library
    • SMIC 0.18um Logic 1P5M Salicide 1.8V/3.3V process
    • 1.8V core and 3.3V External interface
    • Low area and low cost design using DUP technique
    • Meets the revision 2.2 of PCI local bus specification
  • SMIC 0.18um PCI I/O Cells Library
    • SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V process
    • 1.8V core and 3.3V External interface
    • Meets the revision 2.2 of PCI local bus specification
    • Cell count: 6 cells
  • SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library
    • SMIC 0.13ìm Logic 1P8M Salicide 1.2V/3.3V process
    • 1.2V core and 3.3V external interface
    • Meets revision 2.2 of the PCI local bus specification
    • Cell count: 6 cells
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