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PCIe 3.1 Controller with AXI

Overview

The PCIe 3.1 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 3.1 performance with great design flexibility and ease of integration. It is fully compatible with the PCIe 3.1/3.0 specification. A PCIe 3.1 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller delivers high-bandwidth and low-latency connectivity for demanding applications in data center, edge and graphics.

How the PCIe 3.1 Controller Works

The PCIe 3.1 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 3.1/3.0 specifications, as well as the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

The provided Graphical User Interface (GUI) Wizard allows designers to tailor the IP to their exact requirements, by enabling, disabling, and adjusting a vast array of parameters, including data path size, PIPE interface width, low power support, SR-IOV, ECC, AER, etc. for optimal throughput, latency, size and power.

The PCIe 3.1 Controller is verified using multiple PCIe VIPs and test suites, and is silicon proven in hundreds of designs in production. Rambus integrates and validates the PCIe 3.1 Controller with the customer’s choice of 3rd-party PCIe 3.1 PHY.

Key Features

  • PCI Express layer
    • Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
    • Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    • Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
    • Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
    • Supports many ECNs including LTR, L1 PM substates, etc.
  • AMBA AXI layer
    • Compliant with the AMBA® AXI™ Protocol Specification (AXI3, AXI4 and AXI4-Lite) and AMBA® 4 AXI4-Stream Protocol Specification
    • Supports multiple, user-selectable AXI interfaces including AXI Master, AXI Slave, AXI Stream
    • Each AXI interface data width independently configurable in 256-, 128-, and 64-bit
    • Each AXI interface can operate in a separate clock domain
  • Data engines
    • Built-in Legacy DMA engine
      • Up to 8 DMA channels, Scatter-Gather, descriptor prefetch
      • Completion reordering, interrupt and descriptor reporting
    • Optional Address Translation tables for direct PCIe to AXI and AXI to PCIe communication

Block Diagram

PCIe 3.1 Controller with AXI Block Diagram

Applications

  • HPC,
  • Cloud Computing,
  • AI,
  • Machine Learning,
  • Enterprise,
  • Networking,
  • Automotive,
  • AR/VR,
  • Test and Measurement

Deliverables

  • IP files
    • Verilog RTL source code
    • Libraries for functional simulation
    • Configuration assistant GUI
  • Documentation
  • PCI Express Bus Functional Model
    • Encrypted Simulation libraries
  • Software
    • PCI Express Windows x64 and Linux x64 device drivers
    • PCIe C API
  • Reference Designs
    • Synthesizable Verilog RTL source code
    • Simulation environment and test scripts
    • Synthesis project & DC constraint files (ASIC)
    • Synthesis project & constraint files for supported FPGA hardware platforms (FPGA)

Technical Specifications

GLOBALFOUNDRIES
In Production: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
Pre-Silicon: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
Silicon Proven: 28nm SLP , 40nm LP , 55nm , 65nm , 65nm LP , 65nm LPe , 90nm , 90nm LP , 130nm , 130nm HP , 130nm LP , 130nm LV
Renesas
In Production: 40nm , 55nm , 90nm
Pre-Silicon: 40nm , 55nm , 90nm
Silicon Proven: 40nm , 55nm , 90nm
SMIC
In Production: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
Pre-Silicon: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
Silicon Proven: 40nm LL , 55nm G , 55nm LL , 65nm LL , 90nm G , 90nm LL , 110nm G , 130nm G , 130nm LL , 130nm LV
TSMC
In Production: 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GOD , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
Pre-Silicon: 28nm HP , 28nm HPL , 28nm HPM , 28nm LP , 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GOD , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
Silicon Proven: 40nm G , 40nm LP , 45nm GS , 45nm LP , 55nm GP , 55nm LP , 65nm G , 65nm GP , 65nm LP , 80nm , 80nm GT , 80nm HS , 90nm G , 90nm GT , 90nm LP , 90nm zzz , 110nm G , 110nm LVP , 130nm G , 130nm LP , 130nm LV , 130nm LVOD
UMC
In Production: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
Pre-Silicon: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
Silicon Proven: 40nm , 40nm LP , 65nm LL , 65nm LP , 65nm SP , 90nm G , 90nm LL , 90nm SP
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