High-speed IP for GLOBALFOUNDRIES

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Compare 33 High-speed IP for GLOBALFOUNDRIES from 11 vendors (1 - 10)
  • GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
    • The 2.5Gbps LVDS transceiver in GlobalFoundries LP/LP+ is designed for high-speed, low-power data transmission in radiation-intensive environments.
    • Engineered with a Rad-Hard by Design approach, the Rad-Hard cells have been proton tested to 64 MeV with a flux exceeding 1.3E+09, and is latch-up proven to 200mA across -40C to 125C, ensuring robust immunity against TID, SEE, and SEL effects.
    Block Diagram -- GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
  • GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
    • This SLVS I/O Library delivers a robust, high-performance solution for high-speed differential signaling in GlobalFoundries 12nm process technology.
    • Designed for optimal signal integrity, this 0.8V SLVS transceiver features fast rise and fall times, low propagation delay, and built-in pre-emphasis to enhance signal quality over longer traces.
    • With support for data rates up to 3Gbps, it enables reliable, low-power communication while maintaining excellent noise immunity.
    Block Diagram -- GF12 - 0.8V SLVS Rad-Hard Transceiver in GF 12nm
  • Automotive Grade 1 – Differential Output Driver on GLOBALFOUNDRIES 22FDX-AG1
    • Differential output to chip core
    • Wide frequency range support up to 2000MHz output for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
    Block Diagram -- Automotive Grade 1 – Differential Output Driver on GLOBALFOUNDRIES 22FDX-AG1
  • LVDS interfaces
    • Wide operating range
    • High data rates
    • Very flexible programmability
    • Excellent signal integrity
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    Block Diagram -- LVDS interfaces
  • LVDS/FPD Link IP, Silicon Proven in GF 28LPe
    • LVDS compliant Tx
    • 4 groups of 4-Data
    • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
    • Differential polarity can be flip per lane
    Block Diagram -- LVDS/FPD Link IP, Silicon Proven in GF 28LPe
  • LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
    • LVDS compliant Tx
    • 4 groups of 4-Data
    • 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
    • Differential polarity can be flip per lane
    Block Diagram -- LVDS/FPD Link IP, Silicon Proven in GF 65/55LPe
  • Block Diagram -- LVDS RX & TX IOs in multiple foundry technology
  • 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
    • 25-180 MHz clock support
    • Up to 1.25 Gbps bandwidth
    • Up to 5.0 Gbps data throughput
    • Low power CMOS design
    Block Diagram -- 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
  • LVDS IO Pad Set
    • Powered from 1.8V ±10% and 1.0V (±10%) to 1.1V (-10%/+5%) core power supplies
    • Operates up to 1.2GHz (2.4Gbps)
    • Input receive sensitivity of 75mV peak differential (without hysteresis)
    • Common mode range from 0V to 2.4V (limited by Power Supply)
    Block Diagram -- LVDS IO Pad Set
  • 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
    • 25-180 MHz clock support
    • Up to 1.25 Gbps bandwidth
    • Up to 5.0 Gbps data throughput
    • Full Low power CMOS design
    Block Diagram -- 1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
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