Certus provides full LVDS RX & TX IOs in GlobalFoundries and other foundry technologies. The Certus LVDS solutions are ANSI/TIA/EIA-644-A compliant and are capable of data rates of up to 1.5Mbps. Unique to the Certus LVDS solution is that it is self-biased with no external reference blocks required. Our LVDS cell configurations also allow for flexible supply pad arrangements and dense IO placement without compromising signal integrity.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we address standard ESD such as HBM and CDM, but we can also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, SD, I2C, SMBUS, DDC, Analog/RF, HV and other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features to suit your needs.
LVDS RX & TX IOs in multiple foundry technology
Overview
Key Features
- LVDS TX
- Output enable
- Internally generated common mode reference (no external pin required)
- Power-on sequence independence
- ESD protection of 2KV HBM, 500V CDM
- LVDS RX
- Input enable
- Built-in 100? RX termination resistor
- Fault-safe mode for shorted or open RX pins
- Power-on sequence independence
- ESD protection of 2KV HBM, 500V CDM
Benefits
- Self-biased - no external reference required
- Fail-safe
- Flexible pad arrangements
- Power sequence independence
- Proven HBM & CDM ESD protection
Block Diagram
Applications
- LVDS
Deliverables
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Technical Specifications
Foundry, Node
TSMC 130nm, GF 65nm LPE
Maturity
Silicon Proven
Availability
Immediate
GLOBALFOUNDRIES
In Production:
65nm
LPe
Pre-Silicon: 65nm LPe
Silicon Proven: 65nm LPe
Pre-Silicon: 65nm LPe
Silicon Proven: 65nm LPe
TSMC
In Production:
130nm
G
,
130nm
LP
Pre-Silicon: 130nm G , 130nm LP
Silicon Proven: 130nm G , 130nm LP
Pre-Silicon: 130nm G , 130nm LP
Silicon Proven: 130nm G , 130nm LP
Related IPs
- IO & ESD solutions supporting GPIO, I2C,RGMII, SD, LVDS, HDMI & analog/RF across multiple technology nodes
- Voltage reference with multiple output voltages (0.4V to 0.9V) for 3.6V supply, voltage reference sampling capacitor designed in 0.18um 6M TSMC technology.
- LVDS Rx IP, Silicon Proven in GF 28LPe
- MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- Library of LVDS Ios cells in SMIC 130nm~28nm