MIPI DPHY & LVDS Transmit Combo on GF55LPe
Overview
This MIPI DPHY/LVDS Combo Tx PHY IP is designed to the MIPI D-PHY 1.2 specifications and LVDS specifications. This IP supports up to 1.5Gbps for both MIPI and LVDS data rate. This IP can be applied to OpenLDI v0.95 also. This IP includes two PLLs. One is a generic PLL for MIPI clock generation, and the other is an X8/X7 multiplier PLL for serial clock generation.
Key Features
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
- Consists of 6 lanes configurable to be 4+1 MIPI and 7 lanes LVDS
- Supports HS mode (80Mbps to 1.5Gbps) and LS mode (up to 10Mbps) for MIPI mode
- Support up to 1.5Gbps LVDS with 7:1 serializer
- Integrated control interface logic to supports PHY Protocol Interface (PPI)
- Configurable analog characteristics
- Differential voltage
- Common mode voltage
- PLL divider/loop filter
- Support at-speed loopback BIST
- 2.5V/1.2V power supply
- Support GlobalFoundry 55nm LPe process
Block Diagram
Deliverables
- Verilog RTL or netlist source code of lane control unit
- Liberty timing models for synthesis and STA
- Timing constrains for synthesis and physical layout
- Verilog behavior model of PHY part
- Physical design database
- Integration guidelines
Technical Specifications
Foundry, Node
GF, 55nm LPe
Maturity
in development
GLOBALFOUNDRIES
Pre-Silicon:
55nm