Arithmetic & Logic Unit IP
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Parameterizable pipelined multiplier
- Synthesizeable, technology-independent IP Core for FPGA/ASIC and SoC
- Coded with SystemVerilog
- Wrapped with AXI Stream interface
- 16-bit Fixed-Point Representation/Operation
- Suitable for DSP or Machine Learning Applications
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Additive White Gaussian Noise Generator
- High precision AWGN Channel emulator.
- Programmable Pseudo Random Generator(LFSR).
- Programmable number of output bits.
