SynopsysLPDDR5/4/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs.
The controller connects to the Synopsys LPDDR5/4/4X PHY or other LPDDR5/4/4X PHYs via the DFI 5.0 interface to create a complete memory interface solution. The Synopsys LPDDR5/4/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY
LPDDR5/4/4X Controller with Inline Memory Encryption (IME) Security Module
Overview
Key Features
- Complete, integrated LPDDR5/4/4X solution from a single vendor when combined with Synopsys’ DesignWare LPDDR5/4/4X PHY IP
- Supports LPDDR5, LPDDR4, and LPDDR4X protocols
- DDR PHY Interface (DFI) support for easy integration with industry standard DFI 5.0 compliant PHYs
- Up to 16 configurable AMBA ports (4 AXI/3 AXI)
- Enables system designers to extend QoS control into the memory controller
- Supports a host interface slave for easy integration with an external arbiter or non-AMBA on-chip buses Efficient DDR protocol implementation leveraging out-of-order transactions to maximize data throughput, while ensuring starvation avoidance and guaranteeing data coherency
- Read Reorder Buffer (RRB) substantially improves bandwidth while preserving AXI ordering rules
- Inline ECC with scrubbing capability – In-line ECC function provides error correction in systems that cannot use sideband ECC
- Link ECC for LPDDR5
- APB interface for software accessible registers
Benefits
- Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to DesignWare LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
- Best in class performance with unique features such as QoS based scheduling, inline ECC, and dual-channel support
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
- UVM testbench with embedded assertions and options to incorporate a LPDDR5/4/4X PHY into a verification environment
Applications
- Mobile multimedia
- Embedded applications
- Automotive systems
- Smartphones
- Ultraportable laptops
- Embedded mobile computing
Deliverables
- Executable.run installation file which includes: – Custom-configured RTL source code (using Synopsys’ coreConsultant or coreAssembler tool) – Synthesis, design-for-test, and power reduction scripts – SystemVerilog verification environment containing sample integrations of the LPDDR5/4/4X Controller with the DesignWare LPDDR5/4/4X PHY and sample test cases – Performance evaluation test case to enable the user to evaluate performance using their own traffic patterns
- Databook (PDF)
- Release notes (PDF)
- coreConsultant/coreAssembler tools to generate RTL
- Optional Functional Safety Package including DFMEA analysis
- Optional add-on Synopsys Platform Architect
Technical Specifications
Maturity
Available
Availability
Available
Related IPs
- Inline Memory Encryption (IME) Security Module for DDR/LPDDR
- LPDDR5X/5/4X Controller with Inline Memory Encryption (IME) Security Module
- PCIe 5.0 Integrity and Data Encryption Security Module
- CXL 2.0 Integrity and Data Encryption Security Module
- PCIe 6.0 Integrity and Data Encryption Security Module
- DDR4 Memory Controller IP with high performance