The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs. The controller connects to the LPDDR5/4/4X PHY or other LPDDR5/4/4X PHY via the DFI 5.0 interface to create a complete memory interface solution. The LPDDR5/4/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface.
The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY.
The LPDDR Controller seamlessly integrates the Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. The Secure LPDDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the secure memory controllers is as low as 2 clock cycles.
