LPDDR Controller ASIL B Compliant for LPDDR5X/5/4X for automotive
Overview
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. The controller connects to the Synopsys LPDDR5X/5/4X PHY or other LPDDR5X/5/4X PHYs via the DFI 5.0 interface to create a complete memory interface solution. The Synopsys LPDDR5X/5/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual-channel support, as well as the DFI interface to the PHY. The Synopsys LPDDR5X/5/4X Controller seamlessly integrates with the Synopsys Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory.
Key Features
- Complete, integrated LPDDR5X/5/4X solution from a single vendor when combined with Synopsys’ LPDDR5X/5/4X PHY IP
- Supports LPDDR5X, LPDDR5 and LPDDR4X protocols
- DDR PHY Interface (DFI) support for easy integration with industry standard DFI 5.0 compliant PHYs
- Up to 16 configurable AMBA ports (AXI 4/AXI 3)
- Enables system designers to extend QoS control into the memory controller
- Supports a host interface port for easy integration with an external arbiter or non-AMBA on-chip buses
- Efficient DDR protocol implementation leveraging out-of-order transactions to maximize data throughput, while ensuring starvation avoidance and guaranteeing data coherency
- Read Reorder Buffer (RRB) substantially improves bandwidth while preserving AXI ordering rules
- Inline ECC with scrubbing capability – In-line ECC function provides error correction in LPDDR based systems
- Link ECC for LPDDR5X and LPDDR5
- APB interface for software accessible registers
- Optional IME Security Module for LPDDR5X/5/4X Controller
Benefits
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
- DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
- Best in class performance with unique features such as QoS based scheduling, inline ECC, and dual-channel support
- High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
- UVM testbench with embedded assertions and options to incorporate a LPDDR5X/5/4X PHY into a verification environment
- Integrated with Synopsys Inline Memory Encryption (IME) to provide data confidentiality
Applications
- Mobile multimedia
- Embedded applications
- Automotive systems
- Smartphones
- Ultraportable laptops
- Embedded mobile computing
Deliverables
- Executable .run installation file
- Databook (PDF)
- Release notes (PDF)
- coreConsultant/coreAssembler tools to generate RTL
- Optional Functional Safety Package including DFMEA analysis.
- Optional add-on Synopsys Platform Architect
Technical Specifications
Maturity
Available on request
Availability
Available
Related IPs
- 32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- LPDDR Controller ASIL B Compliant for LPDDR5/4/4X for Automotive Applications
- ISO/IEC 7816-3 digital controller for interface device compliant with ETSI TS 102 221 and EMV 2000 standards
- ISO/IEC 7816-3 digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
- DDR and LPDDR 5/4/3/2 controllers for low power and high Reliability, Availability and Serviceability (RAS) targeting automotive
- DDR4 / DDR3/ DDR3L / LPDDR4 Memory Controller IP optimized for low latency