LPDDR5X/5/4X Controller with Inline Memory Encryption (IME) Security Module

Overview

Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs. The controller connects to the Synopsys LPDDR5X/5/4X PHY or other LPDDR5X/5/4X PHYs via the DFI 5.0 interface to create a complete memory interface solution. The Synopsys LPDDR5X/5/4X Controller includes software configuration registers, which are accessed through an AMBA 3.0 APB interface. The LPDDR controller block includes the advanced command scheduler, memory protocol handler, optional inline ECC (Error-correcting code), and dual channel support, as well as the DFI interface to the PHY.

The Synopsys LPDDR Controller seamlessly integrates with the Synopsys Inline Memory Encryption (IME) Security Module to provide confidentiality of data in-use or stored in off-chip memory. Synopsys Secure LPDDR Controller IP supports data confidentiality with standards-compliant independent cryptographic support for read/write channels, per region encryption/decryption and is highly optimized for area, performance and latency. The encryption/decryption latency overhead for the Synopsys secure memory controllers is as low as 2 clock cycles.

Key Features

Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other
LPDDR5X/5/4X PHYs
Best in class performance with unique features such as QoS based scheduling, inline ECC, and dual-channel support
High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes, latency as low as 8 clock cycles
UVM testbench with embedded assertions and options to incorporate a
LPDDR5X/5/4X PHY into a verification environment
Integrated with Synopsys Inline Memory Encryption (IME) to provide data
confidentiality

Applications

Mobile multimedia
Embedded applications
Automotive systems
Smartphones
Ultraportable laptops
Embedded mobile computing

Deliverables

Deliverables
Executable .run installation file which includes:Custom-configured RTL source code (using Synopsys’ coreConsultant or coreAssembler tool); Synthesis, design-for-test, and power reduction scripts; SystemVerilog verification environment containing sample integrations of the LPDDR5/4/4X Controller with the Synopsys LPDDR5x/5 PHY and sample test cases; Performance evaluation test case to enable the user to evaluate performance using their own traffic patterns
Databook (PDF)
Release notes (PDF)
coreConsultant/coreAssembler tools to generate RTL
Optional Functional Safety Package including DFMEA analysis.
Optional add-on Synopsys Platform Architect

Technical Specifications

Maturity

Available on request

Availability

Available

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