LPDDR Controller ASIL B Compliant for LPDDR5/4/4X for Automotive Applications

Overview

Key Features

• Complete, integrated LPDDR5/4/4X solution from a single vendor when combined with Synopsys’ LPDDR5/4/4X PHY IP
• Supports LPDDR5, LPDDR4, and LPDDR4X protocols
• DDR PHY Interface (DFI) support for easy integration with industry standard DFI 5.0 compliant PHYs
• Up to 16 configurable AMBA ports (4 AXI/3 AXI)
• Enables system designers to extend QoS control into the memory controller
• Supports a host interface port for easy integration with an external arbiter or non-AMBA on-chip buses
• Efficient DDR protocol implementation leveraging out-of-order transactions to maximize data throughput, while ensuring starvation avoidance and guaranteeing data coherency
• Read Reorder Buffer (RRB) substantially improves bandwidth while preserving AXI ordering rules
• Inline ECC with scrubbing capability: In-line ECC function provides error correction in systems that cannot use sideband ECC
• Link ECC for LPDDR5
• APB interface for software accessible registers

Benefits

• Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
• Multiport Arm® AMBA® interface (AXI™4/ AXI™3) with managed QoS or single-port host interface to the DDR controller
• DFI 5.0 compliant interface to DesignWare LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
• Best in class performance with unique features such as QoS based scheduling, inline ECC, and dual-channel support
• High-bandwidth design with up to 64 CAM entries for reads and 64 CAM entries for writes; latency as low as 8 clock cycles
• UVM testbench with embedded assertions and options to incorporate a LPDDR5/4/4X PHY into a verification environment
• Integrated with Synopsys Inline Memory Encryption (IME) Security Module to provide data confidentiality

Applications

• Mobile multimedia
• Embedded applications
• Automotive systems
• Smartphones
• Ultraportable laptops
• Embedded mobile computing

Deliverables

• Executable.run installation file which includes:
• Custom-configured RTL source code (using Synopsys’ coreConsultant or coreAssembler tool)
• Synthesis, design-for-test, and power reduction scripts
• SystemVerilog verification environment containing sample integrations of the Synopsys LPDDR5/4/4X Controller with the Synopsys LPDDR5/4/4X PHY and sample test cases: Performance evaluation test case to enable the user to evaluate performance using their own traffic patterns
• Databook (PDF)
• Release notes (PDF)
• coreConsultant/coreAssembler tools to generate RTL
• Optional Functional Safety Package including DFMEA analysis.
• Optional add-on Synopsys Platform Architect

Technical Specifications