Four Channel (4CH) LVDS Receiver in TSMC 40LP

Overview

The MXL-LVDS-4CH-RX-T-40LP is a high-performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock frequency is up to 143MHz. The Receiver is highly integrated and requires no external components. Great care was taken to ensure matching between the Data and Clock channels to maximize the receiver margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

Key Features

Compatible with TIA/EIA-644 LVDS Standard
Consists of 1 Clock lane and up to 4 Data lanes
Up to 1.0 Gbps bandwidth per channel
Up to 4.0 Gbps data throughput
Up to 100MHz in 10 bits mode and 143MHz in 7 bits mode clock support
7/10-bit programmable serial data transmitted per pixel clock per channel

Benefits

LVDS RX IP available in TSMC 40LP

Block Diagram

Applications

Mobile
Displays
Cameras/Sensors
IoT
VR/AR/MR
Consumer electronics
Automotive

Deliverables

Specifications
GDSII
LVS netlist
LEF file
IBIS Model
Verilog Model
Timing Model
Integration Guidelines
RTL
Documentation
One year support

Technical Specifications

Foundry, Node

TSMC, 40LP

Maturity

Available Upon Request

Availability