Four Channel (4CH) LVDS in TSMC 40LP
Overview
The MXL-LVDS-4CH-TX-T-40LP is a high-performance 4-channel LVDS transmitter implemented using digital CMOS technology. With a maximum transmit clock frequency of 143 MHz, it converts 28/40 bits of CMOS data into four LVDS data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. The circuit is designed in a modular fashion and desensitized to process variations resulting in a robust design.
Key Features
- Compatible with TIA/EIA-644 LVDS Standard
- 175 Mbps - 1000 Mbps bandwidth/channel
- Up to 4 Gbps data throughput
- 7-bit/10-bit serial data transmitted per pixel clock per channel
- 4 data channels and 1 clock channel
- PLL requires no external components
Benefits
- LVDS TX IP available in TSMC 40LP
Block Diagram
Applications
- Mobile
- Displays
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TSMC, 40LP
Maturity
Available Upon Request
Availability
Available Upon Request
Related IPs
- Four Channel (4CH) LVDS Receiver in TSMC 40LP
- 1.25 Gbps Four-Channel (4CH) LVDS Serializer with Pre-emphasis
- LVDS serdes 28:4 channel compression TX 20-170Mhz
- LVDS serdes 4:28 channel decompression RX 8-150Mhz
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- Dual FPD-link Transmitter, 30/24-bits color, 40-170 Mhz (SVGA/HDTV@120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression