LVDS receiver, 650M, 5 channel

Overview

Key Features

• Function compatible with the National DS90CF386
• Converts 5-pair LVDS data streams into parallel 35 bits of CMOS/TTL data
• Converts 10-pair LVDS data streams into parallel 70 bits of CMOS/TTL data with double channel
• Wide dot clock range: 25-170MHz suited for VGA, SVGA, XGA, SXGA, SXGA+ and UXGA
• Supports Dual Link at up to 170MHz dot clock for UXGA
• On-chip DLL requires no external component
• Low-power CMOS design
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Full industrial operating temperature range -40 ~ +85 °C
• SMIC 0.18um Logic Salicide Process (1p4m, 1.8V/3.3V)
• Off chip 100ohm resistances between receiver’s positive input and negative input
• Negative clock edge for data output

Technical Specifications