IP Catalog > Analog IP > DLL IP > 4-GHz Jitter-optimized low-power digital PLL

4-GHz Jitter-optimized low-power digital PLL

Overview

Perceptia’s DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV post-scaler. pPLL03 is currently in silicon in the Silterra 180G, ON Semi 180, GlobalFoundries 65LPe, and TSMC 65LP processes.

Key Features

  • Jitter below 10-ps
  • Super small: 90 x 90 microns!
  • Very low power: 15-mW
  • Broad frequency range: 4-GHz
  • Fast lock
  • Lock detect
  • Preprogrammed loop filter
  • BIST
  • Scan testable
  • Power-down mode
  • Decoupling caps for lower jitter
  • Available with companion LDO regulator IP

Deliverables

  • Detailed datasheet including guidance for layout, packaging and production test
  • Characterization report or post-layout corner simulation report
  • LEF abstract for floor planning/chip assembly
  • GDSII layout macrocell
  • Spice/CDL netlist (encrypted format) for LVS
  • DRC / SI verification report
  • Verilog model
  • Timing model (.lib)
  • Test vectors and test guidelines
  • Integration support

Technical Specifications

Foundry, Node
28 - 180-nm
Availability
Now
SMIC
Pre-Silicon: 55nm G , 55nm LL , 65nm LL
TSMC
Silicon Proven: 55nm FL , 55nm G , 55nm GP , 55nm LP , 55nm NF , 55nm ULP , 55nm ULPEF , 55nm UP , 65nm G , 65nm GP , 65nm LP
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