IP Catalog > Analog IP > Clocking IP > DLL IP

DLL IP

Welcome to the ultimate DLL IP hub! Explore our vast directory of DLL IP.

DLL stands for Delay Locked Loops. A Delay Locked Loop IP core refers to a digital feedback circuit wherein there is no use of an oscillator, but instead a delay line is employed as the output is phase locked to an input.

All offers in DLL IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (753)
Compare 753 DLL IP from 14 vendors (1 - 10)
  • Master/Slave DLL
    • The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing
    • This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint
    • The DLL PHY is designed to generate precise phase-shifted clocks (e.g
    • 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission
    Block Diagram -- Master/Slave DLL
  • 800/1000 MHz DLL-based frequency multiplier
    • TSMC 90 nm CMOS
    • Low jitter
    • Precisely aligns the clock distribution output with a reference clock
    • Low current consumption
    Block Diagram -- 800/1000 MHz DLL-based frequency multiplier
  • 30-200 MHz DLL-based frequency multiplier
    • TSMC CMOS 55 nm
    • 30 – 200 MHz output frequency
    • 7.5 – 100 MHz reference frequency
    • Multiplication factor 1, 2, 3 or 4
    • Glitch-free mode switching
    Block Diagram -- 30-200 MHz DLL-based frequency multiplier
  • 10 to 200 MHz DLL-based frequency multiplier
    • Global Foundries CMOS 55 nm
    • 10 – 200 MHz output frequency
    • 0.01 – 100 MHz reference frequency
    • Glitch-free mode switching
    Block Diagram -- 10 to 200 MHz DLL-based frequency multiplier
  • CC-100IP-PI Power Integrity Enhancement IP
    • Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
    • Up to a 36% Dynamic Power and RF Emissions Reduction
    • On-Chip Cybersecurity Enhancement
    • 25% Reduction in Capacitor ESL
    Block Diagram -- CC-100IP-PI Power Integrity Enhancement IP
  • Low Voltage, Low Power Fractional-N PLL
    • GlobalFoundries GF22FDX
    • Small size (< 0.005 sq mm)
    • Low Power (< 0.7mW)
    Block Diagram -- Low Voltage, Low Power Fractional-N PLL
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP for 5G, WiFi, etc
  • High Performance Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX for 5G, WiFi, etc
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX for 5G, WiFi, etc
  • Delay Locked Loop IP
    • Timing resolution: 80ps
    • Operating frequency range: 160MHz – 700 MHz
    • Lock time: 11 cycles
    • Generates user configurable precise phase shifts from 00 to 3600 with a resolution of 10
    Block Diagram -- Delay Locked Loop IP
×
Semiconductor IP