Terminus Circuits offers High speed, low Jitter PLL with 1.25GHz to 2.5GHz output. The ring oscillator based PLL provides balanced quadrature output.
A reset sequence is designed to achieve phase lock on power up or mode change.
The PLL needs a dedicated power supply to reduce the effect of supply noise on it.
Feedback division ratio (N) of 20 – 25.
The frequency output is applicable for multiple protocols.
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
Overview
Key Features
- Type II, 3rd order low Jitter PLL
- Auto calibration for process and temperature (USP)
- Programmable frequency using CSR registers
- 2.5 GHz and 1.25 GHz quadrature clocks
- Operating temperature -40oC to 125 oC
- Standby / power down mode
- Low silicon surface
Benefits
- Ring Oscillator based VCO
- Low area
- Works in two modes - Normal and Power Down
Applications
- Clock multiplication
- Clock for High speed generators for SerDes PHY
- Clock Recovery
Deliverables
- GDS II Layouts
- LEF abstracts
- CDL netlists
- Liberty timings
- Verilog description
- A full datasheet
- An integration note
Technical Specifications
Short description
Low Jitter 1.25GHz to 2.5GHz Quadrature Output PLL
Vendor
Vendor Name
Foundry, Node
TSMC 65nm GP, TSMC 55nm LP, TSMC 28nm, GF 28nm, Samsung 28nm
Maturity
Silicon validated, Pre-silicon
Availability
Now
TSMC
Pre-Silicon:
90nm
LP
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