Low Jitter Digital PLL – 1.25G/2.5G/5G

Overview

The Multiband Quadrature frequency synthesizer generates three frequencies 1.25G / 2.5G / 5G. The frequency outputs is applicable for USB 3.0 / 3.1 and WiFi Transceivers.

Key Features

  • Type II, 3rd order low jitter PLL
  • Auto calibration for process and temperature
  • Programmable frequency using CSR registers
  • 1.25GHz/2.5GHz/5GHz quadrature clocks
  • Operating temperature -40 to 125
  • Standby / power down mode
  • Low silicon surface

Applications

  • Clock multiplication
  • Clock for High speed generators for SerDes PHY
  • Clock Recovery

Deliverables

  • GDS II Layouts
  • LEF abstracts
  • CDL netlists
  • Liberty timings
  • Verilog description
  • Datasheet
  • Integration note

Technical Specifications

Short description
Low Jitter Digital PLL – 1.25G/2.5G/5G
Vendor
Vendor Name
Foundry, Node
TSMC 65nm GP, TSMC 55nm LP, TSMC 28nm, GF 28nm, Samsung 28nm
Maturity
Silicon validated, Pre-silicon
Availability
Now
TSMC
Pre-Silicon: 90nm LP
×
Semiconductor IP