Perceptia’s DeepSub pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV post-scaler. pPLL03 is currently in silicon in the Silterra 180G and GlobalFoundries 65LPe processes.
1.5-GHz Jitter-optimized low-power digital PLL
Overview
Key Features
- Jitter below 20-ps
- Super small: 250 x 250 microns!
- Very low power: 36-mW
- Broad frequency range: 1.5-GHz
- Fast lock
- Lock detect
- Preprogrammed loop filter
- BIST
- Scan testable
- Power-down mode
- Decoupling caps for lower jitter
- Available with companion LDO regulator IP
Deliverables
- The pPLL03 series PLL macros are delivered with:
- Detailed datasheet including guidance for layout, packaging and production test
- Characterization report or post-layout corner simulation report
- LEF abstract for floor planning/chip assembly
- GDSII layout macrocell
- Spice/CDL netlist (encrypted format) for LVS
- DRC / SI verification report
- Verilog model
- Timing model (.lib)
- Test vectors and test guidelines
- Integration support
Technical Specifications
Foundry, Node
28 - 180-nm
Availability
Now
Silterra
Pre-Silicon:
90nm
,
130nm
Silicon Proven: 180nm
Silicon Proven: 180nm
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